The present disclosure relates generally to nanoscale structures, and more particularly, to structures including electrode pairs having a sub-lithographic pitch (i.e., less than 80 nm) and contact pads interconnecting the electrode pairs and methods of manufacturing the same.
Closely spaced electrode pairs have been used for a variety of applications including sensing or electrical characterization of molecules or materials, nonvolatile memory cells such as phase-change memory (PCM) or resistive random-access memory (RRAM) bridge cells, or as defect monitoring structures. Fabrication of electrode pairs with precisely controlled interelectrode gaps less than 20 nm is challenging due to the limitations of patterning technology. In addition, fanning these closely spaced electrode lines out to enable electrical testing is also very challenging. Structures for providing such electrode pairs having a sub-lithographic pitch and electrical contacts that interconnect the electrode pairs are thus desired.